1. Field of the Invention
The present invention relates to a programmable logic array and, more particularly, a programmable logic array which is excellent in charge share tolerance.
2. Description of the Prior Art
FIG. 4 is a circuit diagram showing a configuration of an AND plane of a programmable logic array (called as "PLA" hereinafter) in the prior art. The AND plane of this PLA comprises p-ch MOS transistors (precharge transistors) P1 to P3 . . . whose one ends are connected to a power supply voltage VDD; n-ch MOS transistors (discharge transistors) N1 to N3 . . . whose one ends are connected to a ground voltage GND; a plurality of n-ch MOS transistors (memory cell transistors) N101 to N107 . . . which are series-connected between the precharge transistors P1 to P3 . . . and the discharge transistors N1 to N3 . . . and which constitute an AND plane; output lines BL1 to BL3 . . . of the AND plane; and read buffer cells Buf1 to Buf3 . . . which are connected to the output lines BL1 to BL3 . respectively.
Address lines A11, A11V, A10, A10V, . . . , A0, A0V are input into a plurality of n-ch MOS transistors N101 to N107 . . . constituting the AND plane of the PLA. Where "V" of A11V means an inversion of A11, i.e., A11V means an inverted signal of A11 and this terminology is similarly true of other signals in the following. And, all the series-connected memory cell transistors which are connected to the same output line are turned into their ON states only when a particular address is input thereinto. Accordingly, levels of the output lines BL1 to BL3 . . . of the AND plane can be defined by input signals from the address lines A11, A11V, A10, A10V, . . . , A0, A0V and then these levels are transferred to an OR plane (not shown), for example.
In such AND plane of the PLA, according to a precharge signal PRE serving as a clock, precharge of respective output lines BL1 to BL3 . . . is carried out in a precharge period (PRE="1") as a former half of a clock cycle, and then data are output from respective output lines BL1 to BL3 . . . to the OR plane, etc. in a discharge period (PRE="0") as a latter half thereof.
More particularly, at first, when the precharge signal PRE is shifted to "1" (i.e., PREV="0"), the precharge transistors P1 to P3 . . . which receive PREV at their gates are turned into their ON states. Since one ends of the precharge transistors P1 to P3 . . . are connected to the power supply voltage VDD and the other ends of the precharge transistors P1 to P3 . . . are connected to the output lines BL1 to BL3 . . . , the output lines BL1 to BL3 . . . can be charged up to "1" respectively. The address data can also updated in this precharge period. Since such PREV which are input to gates of the precharge transistors P1 to P3 . . . is also input to gates of the discharge transistors N1 to N3 . . . , there is no case where both the precharge and discharge transistors are turned into their ON states at the same time. For this reason, even if address data to the memory cells are updated such that all the memory cell transistors being connected to the same output line, as described above, are turned into their ON states, no DC route is produced from the power supply voltage VDD to the ground voltage GND in the precharge period.
Next, the precharge signal PRE is shifted to "0" (i.e., PREV="1"), the precharge transistors P1 to P3 . . . are turned into their OFF states and also the discharge transistors N1 to N3 . . . are turned into their ON states. Therefore, the output lines, whose address data are updated such that all the memory cell transistors being connected to such output lines are turned into their ON states, can discharge their holding data "1" to the ground voltage GND via the discharge transistors. In contrast, since connection to the ground voltage GND is cut off via any memory cell transistor being connected to the output lines, the output lines whose address data other than the above address data are updated can still hold the data "1".
In this way, the AND plane of the PLA in the prior art can output information.
However, there have been following problems in the AND plane of the PLA in the prior art. Such problems will be explained with reference to FIGS. 5 and 6 hereinafter.
FIG. 5 is a circuit diagram showing an example of a placement of precharge transistors, memory cell transistors, discharge transistors, and read buffer cells, which are connected to one output line of the AND plane shown in FIG. 4 in the prior art. As shown in FIG. 5, in this example, the memory cell transistors N108 to N119 are placed alternatively every other address line.
In such placement of the memory cell transistors, for example, the case will be discussed where the address data of respective memory cell transistors are updated such that only the memory cell transistor N119 is turned into its OFF state and remaining memory cell transistors N108 to N118 are turned into their ON states. In the case of these address data, as described above, in principle the output line BL4 and drain (source) capacitances of the memory cell transistors N108 to N118 would be charged up to "1" in the precharge period and then "1" would be output from the output line BL4 in the discharge period.
However, as shown in FIG. 6, since the precharge period and the address transition period are overlapped with each other, in case the memory cell transistors N108, N109 positioned in the vicinity of the precharge transistor P4 are turned into their ON states lastly immediately before an end of the precharge period, charging operations of all drain (source) capacitances of the memory cell transistors N108 to N118 cannot be completed in a remaining precharge period (period indicated by t2-t1 in FIG. 6). As a result, charge share is caused and thus the situation that the data held on the output line BL4 is changed from "1" to "0" will be caused. Therefore, essentially the output line has to output "1" but it would output "0", whereby a malfunction of the PLA would be brought about.
Hence, in order to prevent the above mentioned phenomenon, there can be thought out such an approach that, even when the above charge share is caused, the output line BL4 can continue to keep "1" by increasing a parasitic capacitance of the output line BL4, e.g., drain (source) capacitance of the precharge transistor P4. However, this means that a capacitance which must be discharged at the time of reading (in the discharge period) is increased conversely, so that a read rate is widely reduced.
In contrast, in order to carry out the necessary precharge sufficiently, there can be thought out another approach that transition of the address can be finished at the timing which is sufficiently earlier than the end of the precharge period. However, there has been a problem that this approach casts a burden upon a setup time of the address and thus a time used for calculation, etc. must be wasted.